Conventionally, an image memory has been used for processing image data to be displayed. Such an image memory is generally called a Dual Port Dynamic memory or a video RAM. In the following description, an image memory is called a VRAM.
Widely used as a VRAM is a combination of a multi-bit (multi word length) RAM and SAMs of the same number as the multi-bit number. The arrangement of a VRAM having a RAM of 128 k.times.8 bits (capacity: 128 k word-length, 8 bits) is shown in FIG. 7 by way of example. Specifically, there are provided eight planes of RAMs 2 of 256 columns.times.512 rows, and eight SAMs 4 of 256 words .times.1 bit for transferring/receiving data to/from the RAMs. Eight input/output ports, i.e., eight RAM ports 8 and eight SAM ports 8a, are provided respectively for RAMs 2 and SAMs 4.
An example of the arrangement of a frame buffer memory using the VRAM constructed as above is shown in FIG. 8. The frame buffer memory shown in FIG. 8 is assumed to be used with an image screen of 1 k.times.1 k=1 M pixels. The screen image data are constructed of several planes containing color information and the like. In order to speed up the image processing, 4.times.4=16 pixels can be processed during one RAM cycle. Specifically, each pixel of sixteen pixels corresponds to one VRAM, and each plane corresponds to each bit of the multi-bit. Therefore, if sixteen VRAMs are used, it is possible to realize an eight-plane frame buffer memory for 16.times.128 k pixels. In some cases, more than eight planes become necessary. In such a case, one pixel of sixteen pixels may correspond to several VRAMs. For the purpose of simplicity, only a single plane is considered in the following description. A screen image is formed by sixteen VRAMs. In FIG. 8 each pixel is assigned a particular reference number. Pixel data are transferred to every scan line of a CRT in order, from the top of the screen. In this case, the data are serially output from a SAM of VRAM. Considering the first scan line, four VRAMs corresponding to pixels 1, 2, 3 and 4 have the data of this line. In the following description, each VRAMs corresponding to each of the other pixels is assigned a reference number the same as each of the corresponding pixels.
FIG. 9 illustrates the transfer of data of each VRAM to the CRT. A switch 10 shown in FIG. 9 selects a parallel/serial converter 12 or 13. In the parallel/serial converters 12 and 13, data are shifted at the pixel display speed on the CRT. Until such time when all the sets of the first four-pixel data on the top scan line have been transferred from the parallel/serial converter 12 to the CRT, the data in SAM 4 of the VRAMs 1 to 4 are transferred to the parallel/serial converter 13. When there is no more data in the parallel/serial converter 12, the switch 10 is actuated to transfer the data this time from the parallel/serial converter 13. The above operations are repeated until all the data on the first scan line on the image screen have been transferred from the parallel/serial converters 12 and 13, alternately. At the second scan line, instead of the data from VRAMs 1 to 4, the data from VRAMs 5 to 8 are transferred. As described above, the parallel/serial converters 12 and 13 are alternately used to continuously transfer data to the CRT.
As understood from the above-described data transfer method, assuming that the transfer cycle time determined by the image screen pixel display speed is .tau., then it is necessary to set a serial cycle time of the SAM in the VRAM to 4.tau..
Consider that the number of pixels is increased to obtain a finer screen image. FIG. 10 shows the screen size of 2 k.times.2 k=4 M pixels. In order not to change the image processing speed such as the screen image data change speed, the number of pixels to be processed during one cycle of RAM is required to be increased by multiplying by a factor corresponding to an increase of the number of pixels on the image screen. The number of pixels to be processed at a time therefore becomes 8.times.8 =64. In order not to change the screen image display speed irrespective of an increase of the pixel number, it is necessary to change the pixel transfer cycle time to a time divided by the factor, i.e., .tau./4. In the case where the data in VRAMs 1 to 8 shown in FIG. 10 are transferred via eight-pixel parallel/serial converters such as shown in FIG. 9, the serial cycle time of VRAM becomes 8.times..tau./4 =2.tau.. This serial cycle time is half of the 4.tau. required for a 1 M size image screen. The minimum value of the serial cycle time is 30 ns for VRAM that are presently available. If a serial cycle time of 15 ns is required because of an increase of pixels by 4 times for the improvement of an image quality, it is difficult from the viewpoint of current circuit technology to realize VRAM satisfying a serial cycle time of 15 ns. To allow the use of VRAM now available in realizing a finer screen image, a measure to solve this problem has been long desired.